I2S bus

I2S0 master TX stream to the PCM5242 DAC. More...

Collaboration diagram for I2S bus:

Functions
esp_err_t	i2s_bus_init (i2s_chan_handle_t *out_tx_handle)
	Bring up I2S0 as master TX to the PCM5242.
esp_err_t	i2s_bus_reconfig (i2s_chan_handle_t tx, uint32_t rate_hz, uint8_t bits)
	Retune the TX channel for a track: disable, reconfigure clock + slot, re-enable.

Detailed Description

I2S0 master TX stream to the PCM5242 DAC.

Function Documentation

i2s_bus_init()

esp_err_t i2s_bus_init

(

i2s_chan_handle_t *

out_tx_handle

)

Bring up I2S0 as master TX to the PCM5242.

No MCLK is routed; the DAC derives its clock from BCLK. The channel comes up at a default rate/width; the decoder retunes it per track via i2s_bus_reconfig().

Parameters

[out]

out_tx_handle

Receives the enabled TX channel handle.

Returns

ESP_OK on success, or the underlying driver error.

i2s_bus_reconfig()

esp_err_t i2s_bus_reconfig	(	i2s_chan_handle_t	tx,
		uint32_t	rate_hz,
		uint8_t	bits )

Retune the TX channel for a track: disable, reconfigure clock + slot, re-enable.

Both widths ride MSB-justified in a fixed 32-bit slot.

Parameters

tx	TX channel handle from i2s_bus_init().
rate_hz	Sample rate, 8000..192000.
bits	Source sample width; currently ignored — the decoders always emit 32-bit MSB-justified words, so the data width stays 32-bit.

Returns

ESP_OK on success, or the underlying driver error.