audio_dac.c File Reference

#include "audio_dac.h"
#include "i2c_bus.h"

Data Structures
struct	clock_cfg

Macros
#define	PCM5242_ADDR   0x4C
#define	DAC_I2C_TIMEOUT   100 /* ms; fail loud rather than block forever */
#define	REG_PAGE   0x00
#define	REG_STANDBY   0x02 /* RQST=D4 (standby), RQPD=D0 (power-down) */
#define	REG_MUTE   0x03 /* RQML=D4 (left), RQMR=D0 (right); 0 = un-muted */
#define	REG_VOL_CTRL   0x3C /* PCTL[1:0] volume-link mode */
#define	REG_VOL_LEFT   0x3D
#define	REG_VOL_RIGHT   0x3E
#define	REG_CLOCK_STATUS   0x5E /* read-only clock/PLL validity flags (0 = valid) */
#define	STANDBY_REQ   0x10 /* RQST */
#define	MUTE_BOTH   0x11 /* RQML | RQMR */
#define	VOL_INDEPENDENT   0x00 /* PCTL=00: left (0x3D) and right (0x3E) volumes are independent */
#define	REG_CLK_FLAGS   0x25 /* IDSK D4 | IDCH D3 | DCAS D1 (ignore SCK + autoset off) */
#define	REG_PLL_SREF   0x0D /* SREF[2:0]=D6:4: PLL reference clock select */
#define	REG_PLL_P   0x14
#define	REG_PLL_J   0x15
#define	REG_PLL_D_MSB   0x16
#define	REG_PLL_D_LSB   0x17
#define	REG_PLL_R   0x18
#define	REG_DIV_DSP   0x1B /* DDSP: mini-DSP clock divider (NMAC) */
#define	REG_DIV_DAC   0x1C /* DDAC: DAC clock divider (NDAC) */
#define	REG_DIV_NCP   0x1D /* DNCP: charge-pump clock divider (NCP) */
#define	REG_DIV_OSR   0x1E /* DOSR: OSR clock divider (gives OSRCK = 16*fS) */
#define	REG_IDAC_MSB   0x23 /* DSP clock cycles per audio frame (= DSPCLK/fS) */
#define	REG_IDAC_LSB   0x24
#define	CLK_FLAGS_MANUAL   0x1A /* IDSK|IDCH|DCAS: ignore the grounded SCK, drop autoset */
#define	SREF_BCK   0x10 /* SREF[2:0]=001: PLL reference = BCK */
#define	NDAC_FIXED   16 /* DAC clock divider, constant across the supported rates */
#define	NCP_FIXED   4 /* charge-pump clock divider, constant */

Functions
esp_err_t	audio_dac_init (i2c_master_bus_handle_t bus)
	Attach the PCM5242 to the shared I2C bus and select independent L/R volume.
esp_err_t	audio_dac_set_sample_rate (uint32_t rate_hz)
	Retune the PLL and clock dividers for a new sample rate.
esp_err_t	audio_dac_set_volume (uint8_t left, uint8_t right)
	Set the left and right digital volumes independently (see audio_dac_init()).
esp_err_t	audio_dac_get_volume (uint8_t *level)
	Read the left-channel digital volume byte back, for verification.
esp_err_t	audio_dac_mute (bool mute)
	Soft-mute or un-mute both channels (ramped, pop-free).
esp_err_t	audio_dac_standby (bool standby)
	Request or release software standby (DAC and line driver powered down).
esp_err_t	audio_dac_get_clock_status (uint8_t *status)
	Read the clock/PLL status register (0x5E) for bring-up diagnostics.
bool	audio_dac_ready (void)
	Whether the DAC's I2C device is registered (audio_dac_init() has run).

Detailed Description

Note

Développé avec l'assistance de Claude Opus 4.8 (Anthropic), sous la direction de Y. Dos Santos : spécification, revue et validation sur cible par l'auteur.

Macro Definition Documentation

CLK_FLAGS_MANUAL

#define CLK_FLAGS_MANUAL   0x1A /* IDSK|IDCH|DCAS: ignore the grounded SCK, drop autoset */

DAC_I2C_TIMEOUT

#define DAC_I2C_TIMEOUT   100 /* ms; fail loud rather than block forever */

MUTE_BOTH

#define MUTE_BOTH   0x11 /* RQML | RQMR */

NCP_FIXED

#define NCP_FIXED   4 /* charge-pump clock divider, constant */

NDAC_FIXED

#define NDAC_FIXED   16 /* DAC clock divider, constant across the supported rates */

PCM5242_ADDR

#define PCM5242_ADDR   0x4C

REG_CLK_FLAGS

#define REG_CLK_FLAGS   0x25 /* IDSK D4 | IDCH D3 | DCAS D1 (ignore SCK + autoset off) */

REG_CLOCK_STATUS

#define REG_CLOCK_STATUS   0x5E /* read-only clock/PLL validity flags (0 = valid) */

REG_DIV_DAC

#define REG_DIV_DAC   0x1C /* DDAC: DAC clock divider (NDAC) */

REG_DIV_DSP

#define REG_DIV_DSP   0x1B /* DDSP: mini-DSP clock divider (NMAC) */

REG_DIV_NCP

#define REG_DIV_NCP   0x1D /* DNCP: charge-pump clock divider (NCP) */

REG_DIV_OSR

#define REG_DIV_OSR   0x1E /* DOSR: OSR clock divider (gives OSRCK = 16*fS) */

REG_IDAC_LSB

#define REG_IDAC_LSB   0x24

REG_IDAC_MSB

#define REG_IDAC_MSB   0x23 /* DSP clock cycles per audio frame (= DSPCLK/fS) */

REG_MUTE

#define REG_MUTE   0x03 /* RQML=D4 (left), RQMR=D0 (right); 0 = un-muted */

REG_PAGE

#define REG_PAGE   0x00

REG_PLL_D_LSB

#define REG_PLL_D_LSB   0x17

REG_PLL_D_MSB

#define REG_PLL_D_MSB   0x16

REG_PLL_J

#define REG_PLL_J   0x15

REG_PLL_P

#define REG_PLL_P   0x14

REG_PLL_R

#define REG_PLL_R   0x18

REG_PLL_SREF

#define REG_PLL_SREF   0x0D /* SREF[2:0]=D6:4: PLL reference clock select */

REG_STANDBY

#define REG_STANDBY   0x02 /* RQST=D4 (standby), RQPD=D0 (power-down) */

REG_VOL_CTRL

#define REG_VOL_CTRL   0x3C /* PCTL[1:0] volume-link mode */

REG_VOL_LEFT

#define REG_VOL_LEFT   0x3D

REG_VOL_RIGHT

#define REG_VOL_RIGHT   0x3E

SREF_BCK

#define SREF_BCK   0x10 /* SREF[2:0]=001: PLL reference = BCK */

STANDBY_REQ

#define STANDBY_REQ   0x10 /* RQST */

VOL_INDEPENDENT

#define VOL_INDEPENDENT   0x00 /* PCTL=00: left (0x3D) and right (0x3E) volumes are independent */